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Taiwan Semiconductor (TSMC)
0.35 Micron
CL035 (TSMC35_SIL) /
CM035 (TSMC35_P2) Process
1. Process Description
These processes use non-epitaxial wafers. Epitaxial wafers are
available at an additional cost. Specify "epitaxial wafers" in the
"Options" section of the
Request for Custom Quote form
for pricing. To order epitaxial wafers, submit the Request for Custom
Quote and select the epitaxial fabrication option from either the
New Project,
Fabricate, or
Update form.
Both TSMC35_P2 and TSMC35_SIL require Metal 4 in the pad stack. Flip
chip bumping is available from MOSIS. Please send e-mail to
support@mosis.com for more
information.
TSMC35_P2 (CM035)
TSMC35_P2 is the TSMC design technology for the double poly process
(no silicide block). It supports via3 and metal4, and is for 3.3 volt
applications. A thick oxide layer can be used for 5.0 volt
transistors. 5 V ESD is available as an option. PiP (poly2 over
poly) capacitors (850 aF/µm²) are available. Silicide
block is not applicable to this polycided process.
TSMC35_SIL (CL035)
TSMC35_SIL is the TSMC design technology for the single poly,
silicided (with silicide block for diffusion only) process. It
supports 4 metal layers, and is for 3.3 volt applications. A thick
oxide layer can be used for 5.0 volt transistors. 5 V ESD is available
as an option.
2. Design Rules
These processes support the following design rules
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Design Rules
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Lambda
(micro- meter)
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Feature Size
(micro- meter)
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Available From
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SCMOS_SUBM
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0.20
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0.35
(after sizing)
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MOSIS in
HTML
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SCMOS
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0.25
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0.35
(after sizing)
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MOSIS in
HTML
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TSMC rules
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None
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0.35
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MOSIS (See Section 3)
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Note: Stacked contacts/vias are supported by this process.
Review the following
CMP and antenna guidelines which apply to both sets of design
rules.
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MOSIS Technology Codes
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See Technology Codes and Layer Maps for TSMC 0.35 Micron
4 Metal, 2 Poly, Polycide Process
4 Metal, 1 Poly, Silicide Process
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Important note about insulator layers
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On this process, TSMC requires that all features on the insulator
layers (CONTACT, VIA, VIA2, VIA3) be of the single standard size.
There are no exceptions for pads, logos, or anything else. Large
openings are to be replaced by an array of standard sized openings.
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3. TSMC Design Rules, Process Specifications, and SPICE
Parameters
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TSMC has sub-licensed MOSIS to distribute this information to approved
customers who have an account with MOSIS and submit the online
TSMC Access
Request form.
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4. Parametric Test Results and SPICE Model Parameters
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See
Test Results for TSMC_035 runs.
5. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
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TSMC 0.35 Process
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time (weeks, approx.)
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Die Thickness
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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21 x 21 *
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55
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11
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10
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250
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30
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760
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* Smaller sizes are available.
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Related Links
MOSIS-Supported TSMC Processes
TSMC Technology
Codes & Layer Maps
TSMC Document Access
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