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IBM 9LP/9RF CMOS Process
90 Nanometer (90 nm)
If your design will be used for production, i.e. non-MPW, please read
the IBM policy described in
"Checking and
Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 90 nm CMOS 9LP/9RF technology for
prototype and low volume fabrication. This is the low-power variant
of the IBM 90 nm CMOS 9SF technology.
C4 (IBM's flip chip bumping) is subject to availability at additional
cost. Advance notice required: contact
support@mosis.com.
Supply voltages are 1.2 V core and 2.5 V I/O. MOSIS offers this CMOS
process with two distinct metal stacks
A digital stack with 9 metal layers
(M1, M2, M3, M4, M5, M6, M1_2B, M2_2B) and LB topmetal to
DV (glass cut). This is the IBM "9LB_6_02_00_00" stack, with six thin
metals over low-K dielectric, two thick metals ("2x") over TEOS/FTEOS
dielectric, no "4x" metals, LB topmetal, and QT/HT MiM;
An analog stack with 8 metal layers
(M1, M2, M3, M4, M5, M1_2B, OL and LD topmetal to DV (glass cut).
This is the IBM "8LD_5_01_00_01" stack, with five thin metals over
low-K dielectric, one thick metal ("2x") over TEOS/FTEOS dielectric,
no "4x" metals, OL, LD topmetal, and QK/HK MiM.
9LP/9RF Supported Options
Please refer to the
List
of 9LP/9RF Supported Options page for the options available on
MOSIS MPW runs in this technology. You may not submit a design
containing any options or metals stack which are not listed here
without prior arrangement with MOSIS. Note that the QT/HT MiM is used
with the "digital" stack, but QK/HK is used with the "analog" stack.
Other configurations are available for dedicated runs.
Design Considerations
To insure that submitted data is on a 5 nm grid, please stream-out
at 1 DBU = 5 nm (Cadence 0.005, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and
Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to
customers who have signed both the MOSIS customer agreement and the
IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell
libraries, and files listed on the
IBM CMOS Design
Kits page are the only kits and files available.
MOSIS distributes "IBM" as opposed to "CP"
(Common
Platform) design kits.
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
Layouts may be submitted to the 9LP/9RF process using either
technology code IBM_9LP or IBM_9RF. These are absolute synonymns to
MOSIS: "analog" and "digital" stacks may be submitted using either
technology code.
Parametric Test Results and SPICE Model Parameters
See
Test Results for IBM 90 nanometer runs.
Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
IBM CMOS
90 Nanometer
9LP/9RF Process
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time*
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Die Thickness
(+/- .5 mil)
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Bumped Die Thickness **
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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18 x 20
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60
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57
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10
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250
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10
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250
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30
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760
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* Calendar days from release to manufacturing. Does not include
dicing/packaging/backlapping (for planning purposes only).
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe
your requirements in the SPECIAL-HANDLING parameter of your New
Project, Fabrication, or Update Request.
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Related Links
MOSIS-Supported IBM Processes
IBM Technology
Codes & Layer Maps
IBM Document Access
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